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? freescale semiconductor, inc., 20 04, 2005, 2006. all rights reserved. freescale semiconductor data sheet: technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc9328mx1 rev. 7, 12/2006 mc9328mx1 package information plastic package case 1304b-01 (mapbga?225) ordering information see ta b l e 1 on page 3 mc9328mx1 1 introduction the i.mx family of applications processors provides a leap in performance with an arm9? microprocessor core and highly integrated system functions. the i.mx family specifically addresse s the requirements of the personal, portable pro duct market by providing intelligent integrated peripher als, an advanced processor core, and power management capabilities. the mc9328mx1 (i.mx1) pr ocessor features the advanced and power-efficient arm920t? core that operates at speeds up to 200 mhz. integrated modules, which include a usb device, an lcd controller, and an mmc/sd host contro ller, support a suite of peripherals to enhance portable products seeking to provide a rich multimedia experience. it is packaged in a 256-contact mold array process-ball grid array (mapbga). figure 1 shows the functional block diagram of the i.mx1 processor. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 signals and connections . . . . . . . . . . . . . . . 4 3 electrical characteristics . . . . . . . . . . . . . . 22 4 functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 pin-out and package information . . . . . . . . 96 6 product documentation . . . . . . . . . . . . . . . . 98 contact information . . . . . . . . . . . . . . . last page
introduction mc9328mx1 technical data, rev. 7 2 freescale semiconductor figure 1. i.mx1 functional block diagram 1.1 features to support a wide variety of applicatio ns, the processor offers a robust arra y of features, including the following: ? arm920t? microprocessor core ? ahb to ip bus interfaces (aipis) ? external interface module (eim) ? sdram controller (sdramc) ? dpll clock and power control module ? three universal asynchronous receiver/tran smitters (uart 1, uart 2, and uart3) ? two serial peripheral interfaces (spi1 and spi2) ? two general-purpose 32-bit counters/timers ? watchdog timer ? real-time clock/sampling timer (rtc) ? lcd controller (lcdc) ? pulse-width modulation (pwm) module ? universal serial bus (usb) device ? multimedia card and secure digita l (mmc/sd) host controller module ? memory stick? host controller (mshc) ? direct memory access controller (dmac) ? two synchronous serial interfaces and an inter-ic sound (ssi1 and ssi2/i 2 s) module ?inter-ic (i 2 c) bus module ?video port watchdog gpio lcd controller jtag/ice cgm timer 1 & 2 pwm standard bootstrap connectivity system control i 2 c mmc/sd spi 1 and uart 1 uart 2 & 3 usb device smartcard i/f bluetooth memory stick? ssi/i 2 s 1 & 2 analog signal human interface video port multimedia multimedia power rtc bus dmac interrupt vmmu cpu complex i cache aipi 1 aipi 2 d cache esram eim & arm9tdmi? system i/o control (dpllx2) controller control (11 chnl) (128k) sdramc accelerator accelerator processor spi 2 host controller mc9328mx1
introduction mc9328mx1 technical data, rev. 7 freescale semiconductor 3 ? general-purpose i/o (gpio) ports ? bootstrap mode ? analog signal processing (asp) module ? bluetooth? accelerator (bta) ? multimedia accelerator (mma) ? power management features ? operating voltage range: 1.7 v to 1.9 v core, 1.7 v to 3.3 v i/o ? 256-pin mapbga package 1.2 target applications the i.mx1 processor is targeted for advanced information applia nces, smart phones, web browsers, based on the popular palm os platform , and messaging applications such as wireless cellular products, including the accompli tm 008 gsm/gprs interactive communicator . 1.3 ordering information table 1 provides ordering information. 1.4 conventions this document uses the following conventions: ? overbar is used to indicate a signal that is act ive when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conve ys or changes in state convey information. ?a pin is an external physical conne ction. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic level zero to logic level one. table 1. ordering information package type frequency temperature solderball type order number 256-lead mapbga 200 mhz 0c to 70c pb-free mc9328mx1vm20(r2) -30c to 70c pb-free mc9328mx1dvm20(r2) 150 mhz 0c to 70c pb-free mc9328mx1vm15(r2) -30c to 70c pb-free mc9328mx1dvm15(r2) -40c to 85c pb-free mc9328mx1cvm15(r2)
signals and connections mc9328mx1 technical data, rev. 7 4 freescale semiconductor ? negated means that an asserted discre te signal changes logic state. ? active low signals change from logic level zero to logic level one. ? active high signals change from logic level one to logic level zero. ? lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are binary. numbers preceded by a dollar sign ($) or 0x are hexadecimal. 2 signals and connections table 2 identifies and describes the i.mx1 processor signa ls that are assigned to package pins. the signals are grouped by the internal module that they are connected to. table 2. i.mx1 signal descriptions signal name function/notes external bus/chip-select (eim) a[24:0] address bus signals d[31:0] data bus signals eb0 msb byte strobe?active low external enable byte signal that controls d [31:24]. eb1 byte strobe?active low external enable byte signal that controls d [23:16]. eb2 byte strobe?active low external enable byte signal that controls d [15:8]. eb3 lsb byte strobe?active low external enable byte signal that controls d [7:0]. oe memory output enable?active low ou tput enables external data bus. cs [5:0] chip-select?the chip-select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control re gister (fmcr). by default csd [1:0] is selected. ecb active low input signal sent by a flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by a flash device causing the external burst device to latch the starting burst address. bclk (burst clock) clock signal sent to external synchronous memori es (such as burst flash) during burst mode. rw rw signal?indicates w hether external access is a read (high) or write (low) cycle. used as a we input signal by external dram. dtack dtack signal?the external input data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 clock counts have elapsed. bootstrap boot [3:0] system boot mode select?the o perational system boot mode of the i.mx 1 processor upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram non-interleave mode bank address multiplexe d with address signals a [15:11]. these signals are logically equiva lent to core address p_ad dr [25:21] in sdram cycles.
signals and connections mc9328mx1 technical data, rev. 7 freescale semiconductor 5 sdiba [3:0] sdram interleave addressing mode bank address mu ltiplexed with address signals a [19:16]. these signals are logically equivalent to core address p_addr [12:9] in sdram cycles. ma [11:10] sdram address signals ma [9:0] sdram address signals which are multiplexed with a ddress signals a [10:1]. ma [9:0] are selected on sdram cycles. dqm [3:0] sdram data enable csd0 sdram chip-select signal which is multiplexed with the cs2 signal. these two signals are selectable by programming the syst em control register. csd1 sdram chip-select signal which is multiplexed with cs3 signal. these two signals are selectable by programming the system contro l register. by default, csd1 is selected, so it can be used as boot chip-select by properly configuring boot [3:0] input pins. ras sdram row address select signal cas sdram column address select signal sdwe sdram write enable signal sdcke0 sdram clock enable 0 sdcke1 sdram clock enable 1 sdclk sdram clock reset_sf not used clocks and resets extal16m crystal input (4 mhz to 16 mhz), or a 16 mhz oscillator input when the internal oscillator circuit is shut down. xtal16m crystal output extal32k 32 khz crystal input xtal32k 32 khz crystal output clko clock out signal selected fr om internal clock signals. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module and the clock control module) are reset. reset_out reset out?internal active low output signal from th e watchdog timer module and is asserted from the following sources: power-on re set, external reset (reset_in ), and watchdog time-out. por power on reset?internal active high schmitt trig ger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. jtag trst test reset pin?external active low signal used to asynchronously initiali ze the jtag controller. tdo serial output for test instructions an d data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and control register access through the jtag port. tms test mode select to sequence the jt ag test controller?s state machine. sampled on the rising edge of tck. table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 6 freescale semiconductor dma dma_req dma request ?external dma request signal. multiplexed with spi1_spi_rdy. big_endian big endian?input signal that determines the configurat ion of the external chip-select space. if it is driven logic-high at reset, the external chip-select sp ace will be configured to big endian. if it is driven logic-low at reset, the external chip-select space will be configured to little endian. this input must not change state after power-on reset ne gates or during chip operation. etm etmtracesync etm sync signal which is mult iplexed with a24. etmtracesy nc is selected in etm mode. etmtraceclk etm clock signal which is multiplexed with a23. etmtraceclk is selected in etm mode. etmpipestat [2:0] etm status signals which are mu ltiplexed with a [22:20]. etmpipestat [2 :0] are selected in etm mode. etmtracepkt [7:0] etm packet signals which are multiplexed with ecb , lba , bclk (burst clock), pa17, a [19:16]. etmtracepkt [7:0] are selected in etm mode. cmos sensor interface csi_d [7:0] sensor port data csi_mclk sensor port master clock csi_vsync sensor port vertical sync csi_hsync sensor port horizontal sync csi_pixclk sensor port data latch clock lcd controller ld [15:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. flm/vsync frame sync or vsync?this signal also serves as the clock signal output for the gate driver (dedicated signal sps for sharp panel hr-tft). lp/hsync line pulse or h sync lsclk shift clock acd/oe alternate crystal di rection/output enable. contrast this signal is used to control the lcd bias voltage as contrast control. spl_spr program horizontal scan direction (sharp panel dedicated signal). ps control signal output for source driver (sharp panel dedicated signal). cls start signal output for gate driver. this signal is an inverted version of ps (sharp panel dedicated signal). rev signal for common electrode driving signal preparation (sharp panel dedicated signal). sim sim_clk sim clock sim_rst sim reset sim_rx receive data table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 freescale semiconductor 7 sim_tx transmit data sim_pd presence detect schmitt trigger input sim_sven sim vdd enable spi 1 and spi 2 spi1_mosi master out/slave in spi1_miso slave in/master out spi1_ss slave select (selectable polarity) spi1_sclk serial clock spi1_spi_rdy serial data ready spi2_txd spi2 master txdata output?this signal is multiple xed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. please refer to the spi and gpio chapters in the mc9328mx1 reference manual for information about how to bring this signal to the assigned pin. spi2_rxd spi2 master rxdata input?this si gnal is multiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. please refer to the spi and gpio chapters in the mc9328mx1 reference manual for information about how to bring this signal to the assigned pin. spi2_ss spi2 slave select?this signal is multiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. plea se refer to the spi and gpio chapters in the mc9328mx1 reference manual for information about how to bring this signal to the assigned pin. spi2_sclk spi2 serial clock?this signal is multiplexed with a gp i/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. plea se refer to the spi and gpio chapters in the mc9328mx1 reference manual for information about how to bring this signal to the assigned pin. general purpose timers tin timer input capture or timer input clock?the signal on this input is applied to both timers simultaneously. tmr2out timer 2 output usb device usbd_vmo usb minus output usbd_vpo usb plus output usbd_vm usb minus input usbd_vp usb plus input usbd_suspnd usb suspend output usbd_rcv usb receive data usbd_ r oe usb oe usbd_afe usb analog front end enable secure digital interface sd_cmd sd command?if the system designer does not wish to make use of the internal pull-up, via the pull-up enable register, a 4.7k?69k external pull up resistor must be added. table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 8 freescale semiconductor sd_clk mmc output clock sd_dat [3:0] data?if the system designer does not wish to make us e of the internal pull-up, via the pull-up enable register, a 50k?69k external pull up resistor must be added. memory stick interface ms_bs memory stick bus state (output )?serial bus control signal ms_sdio memory stick serial data (input/output) ms_sclko memory stick serial clock (input)?serial protocol clock source for sclk divider ms_sclki memory stick external clock (outpu t)?test clock input pin for sclk divider. this pin is only for test purposes, not for use in application mode. ms_pi0 general purpose input0?can be used for me mory stick insertion/extraction detect ms_pi1 general purpose input1?can be used for me mory stick insertion/extraction detect uarts ? irda/auto-bauding uart1_rxd receive data uart1_txd transmit data uart1_rts request to send uart1_cts clear to send uart2_rxd receive data uart2_txd transmit data uart2_rts request to send uart2_cts clear to send uart2_dsr data set ready uart2_ri ring indicator uart2_dcd data carrier detect uart2_dtr data terminal ready uart3_rxd receive data uart3_txd transmit data uart3_rts request to send uart3_cts clear to send uart3_dsr data set ready uart3_ri ring indicator uart3_dcd data carrier detect uart3_dtr data terminal ready serial audio port ? ssi (configurable to i 2 s protocol) ssi_txdat transmit data ssi_rxdat receive data table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 freescale semiconductor 9 ssi_txclk transmit serial clock ssi_rxclk receive serial clock ssi_txfs transmit frame sync ssi_rxfs receive frame sync ssi2_txdat txd ssi2_rxdat rxd ssi2_txclk transmit serial clock ssi2_rxclk receive serial clock ssi2_txfs transmit frame sync ssi2_rxfs receive frame sync i 2 c i2c_scl i 2 c clock i2c_sda i 2 c data pwm pwmo pwm output asp uin positive u analog input (for low voltage, temperature measurement) uip negative u analog input (for lo w voltage, temperature measurement) px1 positive pen-x analog input py1 positive pen-y analog input px2 negative pen-x analog input py2 negative pen-y analog input r1a positive resist ance input (a) r1b positive resist ance input (b) r2a negative resistance input (a) r2b negative resistance input (b) rvp positive reference for pen adc rvm negative reference for pen adc avdd analog power supply agnd analog ground bluetooth bt1 i/o clock signal bt2 output bt3 input table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 10 freescale semiconductor 2.1 i/o pads power supply and signal multiplexing scheme this section describes detailed in formation about both the power suppl y for each i/o pin and its function multiplexing scheme. the user can reference information provided in table 6 on page 23 to configure the power supply scheme for each device in the system (memory and external peripherals). the function multiplexing information also shown in table 6 allows the user to select the function of each pin by configuring the appropriate gpio registers when those pins are mult iplexed to provide different functions. bt4 input bt5 output bt6 output bt7 output bt8 output bt9 output bt10 output bt11 output bt12 output bt13 output btrf vdd power supply from external bt rfic btrf gnd ground from external bt rfic test function tristate forces all i/o signals to high impedance for test pur poses. for normal operation, terminate this input with a 1 k ohm resistor to ground. (tri-state ? is a registered trademark of national semiconductor.) digital supply pins nvdd digital supply for the i/o pins nvss digital ground for the i/o pins supply pins ? analog modules avdd supply for analog blocks internal power supply qvdd power supply pins for silicon internal circuitry qvss ground pins for silicon internal circuitry table 2. i.mx1 signal descriptions (continued) signal name function/notes
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 11 table 3. mc9328mx1 signal multiplexing scheme i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout nvdd1 k8 nvdd1 static nvdd1 b1 a24 o etmtracesyn c o pa0 69k spi2_clk l a24 nvdd1 c2 d31 i/o 69k pull-h nvdd1 c1 a23 o etmtraceclk o pa31 69k l a23 nvdd1 d2 d30 i/o 69k pull-h nvdd1 d1 a22 o etmpipestat2 o pa30 69k l a22 nvdd1 d3 d29 i/o 69k pull-h nvdd1 e2 a21 o etmpipestat1 o pa29 69k l a21 nvdd1 e3 d28 i/o 69k pull-h nvdd1 e1 a20 o etmpipestat0 o pa28 69k l a20 nvdd1 f2 d27 i/o 69k pull-h nvdd1 f4 a19 o etmtracepkt3 o pa27 69k l a19 nvdd1 e4 d26 i/o 69k pull-h a1 vss static nvdd1 h5 nvdd1 static nvdd1 f1 a18 o etmtracepkt2 o pa26 69k l a18 nvdd1 f3 d25 i/o 69k pull-h nvdd1 g2 a17 o etmtracepkt1 o pa25 69k l a17 nvdd1 g3 d24 i/o 69k pull-h nvdd1 f5 a16 o etmtracepkt0 o pa24 69k l a16 nvdd1 g4 d23 i/o 69k pull-h nvdd1 g1 a15 o l nvdd1 h2 d22 i/o 69k pull-h nvdd1 h3 a14 o l
mc9328mx1 technical data, rev. 7 12 freescale semiconductor signals and connections nvdd1 g5 d21 i/o 69k pull-h nvdd1 h1 a13 o l nvdd1 h4 d20 i/o 69k pull-h t1 vss static qvdd1 h9 qvdd1 static h8 vss static nvdd1 j5 nvdd1 static nvdd1 j1 a12 o l nvdd1 j4 d19 i/o 69k pull-h nvdd1 j2 a11 o l nvdd1 j3 d18 i/o 69k pull-h nvdd1 k1 a10 o l nvdd1 k4 d17 i/o 69k pull-h nvdd1 k3 a9 o l nvdd1 k2 d16 i/o 69k pull-h nvdd1 l1 a8 o l nvdd1 l4 d15 i/o 69k pull-h nvdd1 l2 a7 o l nvdd1 l5 d14 i/o 69k pull-h k6 vss static nvdd1 k5 nvdd1 static nvdd1 m4 a6 o l nvdd1 l3 d13 i/o 69k pull-h nvdd1 m1 a5 o l nvdd1 m2 d12 i/o 69k pull-h table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 13 nvdd1 n1 a4 o l nvdd1 m3 d11 i/o 69k pull-h nvdd1 p3 eb0 o h nvdd1 n3 d10 i/o 69k pull-h nvdd1 p1 a3 o l nvdd1 n2 eb1 o h nvdd1 p2 d9 i/o 69k pull-h nvdd1 r1 eb2 o h m6 vss static nvdd1 h6 nvdd1 static nvdd1 t2 a2 o l nvdd1 r2 eb3 o h nvdd1 r5 d8 i/o 69k pull-h nvdd1 t3 oe o h nvdd1 r3 a1 o l nvdd1 t4 cs5 o pa23 69k pull-h pa23 nvdd1 n4 d7 i/o 69k pull-h nvdd1 r4 cs4 o pa22 69k pull-h pa22 nvdd1 n5 a0 o pa21 69k l a0 nvdd1 p4 cs3 ocsd1 hcsd1 nvdd1 p5 d6 i/o 69k pull-h nvdd1 t5 cs2 ocsd0 hcsd0 h7 vss static nvdd1 j6 nvdd1 static nvdd1 m5 sdclk o h table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
mc9328mx1 technical data, rev. 7 14 freescale semiconductor signals and connections nvdd1 t6 cs1 o h nvdd1 t7 cs0 o h 1 nvdd1 r6 d5 i/o 69k pull-h nvdd1 p6 ecb i etmtracepkt7 pa20 69k pull-h ecb nvdd1 n6 d4 i/o 69k pull-h nvdd1 r7 lba o etmtracepkt6 pa19 69k h lba nvdd1 p8 d3 i/o 69k pull-h nvdd1 r8 bclk etmtracepkt5 pa18 69k l bclk nvdd1 p7 d2 i/o 69k pull-h j7 vss static nvdd1 l6 nvdd1 static nvdd1 n7 dtack i etmtracepkt4 pa17 69k spi2_ss a25 pull-h pa17 nvdd1 n8 d1 i/o 69k pull-h nvdd1 m7 rw h nvdd1 t8 ma11 o l nvdd1 m8 ma10 o l nvdd1 r9 d0 i/o 69k pull-h k7 vss static nvdd1 p9 dqm3 o l nvdd1 t9 dqm2 o l nvdd1 n9 dqm1 o l nvdd1 r10 dqm0 o l nvdd1 m9 ras o h nvdd1 l8 cas o h nvdd1 j8 nvdd1 static table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 15 nvdd1 t10 sdwe o h nvdd1 r11 sdcke0 o h nvdd1 p10 sdcke1 o h nvdd1 n10 reset_sf o l/h nvdd1 t11 clko o l l7 vss static avdd1 t12 avdd1 static avdd1 m10 reset_in i 69k l/h 2 avdd1 n11 reset_out o l/h avdd1 r12 por i h/l 2 avdd1 m11 big_endian i hiz 3 avdd1 p11 boot3 i hiz 4 avdd1 n12 boot2 i hiz 4 avdd1 r13 boot1 i hiz 4 avdd1 p12 boot0 i hiz 4 avdd1 t13 tristate i hiz 4 avdd1 p13 trst i 69k h qvdd2 r15 qvdd2 static t16 vss static avdd1 t14 extal16m i hiz avdd1 t15 xtal16m o avdd1 r16 extal32k i hiz avdd1 p16 xtal32k o nvdd2 k10 nvdd2 static table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
mc9328mx1 technical data, rev. 7 16 freescale semiconductor signals and connections nvdd2 r14 tdo o hiz 5 nvdd2 n15 tms i 69k pull-h nvdd2 l9 tck i 69k pull-h nvdd2 n16 tdi i 69k pull-h nvdd2 p14 i2c_scl o pa16 69k pull-h pa16 nvdd2 p15 i2c_sda i/o pa15 69k pull-h pa15 nvdd2 n13 csi_pixclk i pa14 69k pull-h pa14 nvdd2 m13 csi_hsync i pa13 69k pull-h pa13 nvdd2 m14 csi_vsync i pa12 69k pull-h pa12 nvdd2 n14 csi_d7 i pa11 69k pull-h pa11 nvdd2 m15 csi_d6 i pa10 69k pull-h pa10 nvdd2 m16 csi_d5 i pa9 69k pull-h pa9 nvdd2 j10 vss static nvdd2 m12 csi_d4 i pa8 69k pull-h pa8 nvdd2 l16 csi_d3 i pa7 69k pull-h pa7 nvdd2 l15 csi_d2 i pa6 69k pull-h pa6 nvdd2 l14 csi_d1 i pa5 69k pull-h pa5 nvdd2 l13 csi_d0 i pa4 69k pull-h pa4 nvdd2 l12 csi_mclk o pa3 69k pull-h pa3 nvdd2 l11 pwmo o pa2 69k pull-h pa2 nvdd2 l10 tin i pa1 69k spi2_rxd pull-h pa1 nvdd2 k15 tmr2out o pd31 69k spi2_txd pull-h pd31 nvdd2 k16 ld15 o pd30 69k pull-h pd30 nvdd2 k14 ld14 o pd29 69k pull-h pd29 nvdd2 k13 ld13 o pd28 69k pull-h pd28 table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 17 nvdd2 k12 ld12 o pd27 69k pull-h pd27 qvdd3 j15 qvdd3 static j16 vss static nvdd2 k9 nvdd2 static nvdd2 j14 ld11 o pd26 69k pull-h pd26 nvdd2 k11 ld10 o pd25 69k pull-h pd25 nvdd2 h15 ld9 o pd24 69k pull-h pd24 nvdd2 j13 ld8 o pd23 69k pull-h pd23 nvdd2 j12 ld7 o pd22 69k pull-h pd22 nvdd2 j11 ld6 o pd21 69k pull-h pd21 nvdd2 h14 ld5 o pd20 69k pull-h pd20 nvdd2 h13 ld4 o pd19 69k pull-h pd19 nvdd2 h16 ld3 o pd18 69k pull-h pd18 nvdd2 h12 ld2 o pd17 69k pull-h pd17 nvdd2 g16 ld1 o pd16 69k pull-h pd16 nvdd2 h11 ld0 o pd15 69k pull-h pd15 nvdd2 g15 flm/vsync o pd14 69k pull-h pd14 nvdd2 g14 lp/hsync o pd13 69k pull-h pd13 nvdd2 g13 acd/oe o pd12 69k pull-h pd12 nvdd2 g12 contrast o pd11 69k spi2_ss2 pull-h pd11 nvdd2 f16 spl_spr o uart2_dsr o pd10 69k spi2_txd pull-h pd10 nvdd2 h10 ps o uart2_ri o pd9 69k spi2_rxd pull-h pd9 nvdd2 g11 cls o uart2_dcd o pd8 69k spi2_ss pull-h pd8 nvdd2 f12 rev o uart2_dtr i pd7 69k spi2_clk pull-h pd7 nvdd2 f15 lsclk o pd6 69k pull-h pd6 table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
mc9328mx1 technical data, rev. 7 18 freescale semiconductor signals and connections j9 vss static qvdd 6 e16 r2a i qvdd qvdd 6 d16 r2b i qvdd 6 f14 px1 i qvdd 6 f13 py1 i qvdd 6 e15 px2 i qvdd 6 e14 py2 i qvdd 6 d15 r1a i qvdd 6 c16 r1b i c15 vss static avdd2 6 c14 avdd2 static qvdd 6 b16 nc i qvdd 6 a16 nc i qvdd 6 b15 uin i qvdd 6 a15 uip i qvdd 6 e13 nc i qvdd 6 d14 nc i qvdd 6 b14 rvm i qvdd 6 a14 rvp i qvdd 6 d13 nc i qvdd 6 c13 nc i qvdd 6 e12 nc o table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 19 qvdd 6 d12 nc o qvdd4 a13 qvdd4 static b13 vss static btrfvdd c12 btrfvdd static btrfvdd b12 bt1 i pc31 69k uart3_rx pull-h pc31 btrfvdd f11 bt2 o pc30 69k uart3_tx hiz pc30 btrfvdd a12 bt3 i pc29 69k uart3_rts pull-h pc29 btrfvdd e11 bt4 i pc28 69k uart3_cts pull-h pc28 btrfvdd a11 bt5 i/o pc27 69k uart3_dcd pull-h pc27 btrfvdd d11 bt6 o pc26 69k spi2_ss3 uart3_dtr l pc26 btrfvdd b11 bt7 o pc25 69k uart3_dsr lpc25 btrfvdd c11 bt8 o ssi2_rxf s pc24 69k uart3_ri hiz pc24 btrfvdd g10 bt9 o ssi2_rx pc23 69k l pc23 btrfvdd f10 bt10 o ssi2_tx pc22 69k h pc22 btrfvdd b10 bt11 o ssi2_txclk pc21 69k h pc21 btrfvdd e10 bt12 o ssi2_txfs pc20 69k hiz pc20 btrfvdd d10 bt13 o ssi2_rxclk pc19 69k l pc19 c10 btrfgnd static nvdd3 a10 nvdd3 static nvdd3 g9 spi1_mosi i/o pc17 69k pull-h pc17 nvdd3 f9 spi1_miso i/o pc16 69k pull-h pc16 nvdd3 e9 spi1_ss i/o pc15 69k pull-h pc15 nvdd3 b9 spi1_sclk i/o pc14 69k pull-h pc14 nvdd3 d9 spi1_spi_rdy i pc13 69k dma_req pull-h pc13 nvdd3 a9 uart1_rxd i pc12 69k pull-h pc12 table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
mc9328mx1 technical data, rev. 7 20 freescale semiconductor signals and connections nvdd3 c9 uart1_txd o pc11 69k pull-h pc11 nvdd3 a8 uart1_rts i pc10 69k pull-h pc10 nvdd3 g8 uart1_cts o pc9 69k pull-h pc9 nvdd3 b8 ssi_txclk i/o pc8 69k pull-h pc8 nvdd3 f8 ssi_txfs i/o pc7 69k pull-h pc7 nvdd3 e8 ssi_txdat o pc6 69k pull-h pc6 nvdd3 d8 ssi_rxdat i pc5 69k pull-h pc5 nvdd3 b7 ssi_rxclk i/o pc4 69k pull-h pc4 nvdd3 c8 ssi_rxfs i/o pc3 69k pull-h pc3 a7 vss static nvdd4 c7 uart2_rxd i pb31 69k pull-h pb31 nvdd4 f7 uart2_txd o pb30 69k pull-h pb30 nvdd4 e7 uart2_rts i pb29 69k pull-h pb29 nvdd4 c6 uart2_cts o pb28 69k pull-h pb28 nvdd4 d7 usbd_vmo o pb27 69k pull-h pb27 nvdd4 d6 usbd_vpo o pb26 69k pull-h pb26 nvdd4 e6 usbd_vm i pb25 69k pull-h pb25 nvdd4 b6 usbd_vp i pb24 69k pull-h pb24 nvdd4 d5 usbd_suspnd o pb23 69k pull-h pb23 nvdd4 c5 usbd_rcv i/o pb22 69k pull-h pb22 nvdd4 b5 usbd_ ro e o pb21 69k pull-h pb21 nvdd4 a5 usbd_afe o pb20 69k pull-h pb20 a4 vss static nvdd4 a6 nvdd4 static nvdd4 g7 sim_clk o ssi_txclk i/o pb19 69k pull-h pb19 table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
signals and connections mc9328mx1 technical data, rev. 7 reescale semiconductor 21 nvdd4 f6 sim_rst o ssi_txfs i/o pb18 69k pull-h pb18 nvdd4 g6 sim_rx i ssi_txdat o pb17 69k pull-h pb17 nvdd4 b4 sim_tx i/o ssi_rxdat i pb16 69k pull-h pb16 nvdd4 c4 sim_pd i ssi_rxclk i/o pb15 69k pull-h pb15 nvdd4 d4 sim_sven o ssi_rxfs i/o pb14 69k pull-h pb14 nvdd4 b3 sd_cmd i/o ms_bs o pb13 69k pull-h pb13 nvdd4 a3 sd_clk o ms_sclko o pb12 69k pull-h pb12 nvdd4 a2 sd_dat3 i/o ms_sdio i/o pb11 69k (pull down) pull-l pb11 nvdd4 e5 sd_dat2 i/o ms_sclki i pb10 69k pull-h pb10 nvdd4 b2 sd_dat1 i/o ms_pi1 i pb9 69k pull-h pb9 nvdd4 c3 sd_dat0 i/o ms_pi0 i pb8 69k pull-h pb8 1 after reset, cs0 goes h/l depends on boot[3:0]. 2 need external circuitry to drive the signal. 3 need external pull-up. 4 external resistor is needed. 5 need external pull-up or pull-down. 6 asp signals are clamped by avdd2 to prevent esd (electrostatic discharge) damage. avdd2 must be greater than qvdd to keep diode s reverse-biased. table 3. mc9328mx1 signal multiplexing scheme (continued) i/o supply voltage bga pin primary alternate gpio rese state (at/after) default signal dir pull-up signal dir mux pull-up ain bin aout
electrical characteristics mc9328mx1 technical data, rev. 7 22 freescale semiconductor 3 electrical characteristics this section contains the electrical specificati ons and timing diagrams for the i.mx1 processor. 3.1 maximum ratings table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. functional operation should be restricted to the limits listed in recommended operating range table 5 on page 23 or the dc characteristics table. 3.2 recommended operating range table 5 provides the recommended opera ting ranges for the supply voltage s and temperatures. the i.mx1 processor has multiple pairs of vdd and vss power supply and return pins. qvdd and qvss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provides power to the enclosed i/o pads. this design al lows different peripheral supply voltage levels in a system. because avdd pins are supply voltage s to the analog pads, it is recomm ended to isolate and noise-filter the avdd pins from other vdd pins. btrfvdd is the supply voltage for the bluetooth inte rface signals. it is quite sensitive to the data transmit/receive accuracy. pl ease refer to bluetooth rf spec for spec ial handling. if bluetooth is not used table 4. maximum ratings symbol rating minimum maximum unit nv dd dc i/o supply voltage -0.3 3.3 v qv dd dc internal (core = 150 mhz) supply voltage -0.3 1.9 v qv dd dc internal (core = 200 mh z) supply voltage -0.3 2.0 v av dd dc analog supply voltage -0.3 3.3 v btrfv dd dc bluetooth supply voltage -0.3 3.3 v vesd_hbm esd immunity with hbm (human body model) ? 2000 v vesd_mm esd immunity with mm (machine model) ? 100 v ilatchup latch-up immunity ? 200 ma test storage temperature -55 150 c pmax power consumption 800 1 1 a typical application with 30 pads simultaneo usly switching assumes the gpio togglin g and instruction fetches from the arm ? core-that is, 7x gpio, 15x data bus, and 8x address bus. 1300 2 2 a worst-case application with 70 pads simultaneously switching assumes the gpio toggling and instruction fetches from the arm core-that is, 32x gpio, 30x data bus, 8x address bus. t hese calculations are based on the core running its heaviest os application at mhz, and where the whole image is running out of sdram. qvdd at v, nvdd and avdd at 3.3v, therefore, 180ma is the worst measurement recorded in the factory environm ent, max 5ma is consumed for osc pads, with each toggle gpio consuming 4ma. mw
electrical characteristics mc9328mx1 technical data, rev. 7 freescale semiconductor 23 in the system, these bluetooth pins can be used as general purpose i/o pins and btrfvdd can be used as other nvdd pins. for more information about i/o pads grouping per vdd, please refer to table 2 on page 4 . 3.3 power sequence requirements for required power-up and power-dow n sequencing, please refer to th e ?power-up sequence? section of application note an2537 on the i.mx applications processor website. 3.4 dc electrical characteristics table 6 contains both maximum and minimum dc characteristics of the i.mx1 processor. table 5. recommended operating range symbol rating minimum maximum unit t a operating temperature range mc9328mx1vm20\mc9328mx1vm15 070c t a operating temperature range mc9328mx1dvm20\mc9328mx1dvm15 -30 70 c t a operating temperature range mc9328mx1cvm15 -40 85 c nvdd i/o supply voltage (if using mshc, csi, spi, bta, lcd, and usbd which are only 3 v interfaces) 2.70 3.30 v nvdd i/o supply voltage (if not using the peripherals listed above) 1.70 3.30 v qvdd internal supply voltage (core = 150 mhz) 1.70 1.90 v qvdd internal supply voltage (core = 200 mhz) 1.80 2.00 v avdd analog supply voltage 1.70 3.30 v table 6. maximum and minimum dc characteristics number or symbol parameter min typical max unit iop full running operating current at 1.8v for qvdd, 3.3v for nvdd/avdd (core = 96 mhz, system = 96 mhz, mpeg4 decoding playback from external memory card to both external ssi audio decoder and driving tft display panel, and os with mmu enabled memo ry system is running on external sdram). ? qvdd at 1.8v = 120ma; nvdd+avdd at 3.0v = 30ma ?ma sidd 1 standby current (core = 150 mhz, qvdd = 1.8v, temp = 25 c) ?25 ? a sidd 2 standby current (core = 150 mhz, qvdd = 1.8v, temp = 55 c) ?45 ? a sidd 3 standby current (core = 150 mhz, qvdd = 2.0v, temp = 25 c) ?35 ? a
electrical characteristics mc9328mx1 technical data, rev. 7 24 freescale semiconductor 3.5 ac electrical characteristics the ac characteristics consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other signals. all timing specifications are specified at a system operating frequency from 0 mhz to 96 mhz (core operating frequency 150 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at 30 pf loading. sidd 4 standby current (core = 150 mhz, qvdd = 2.0v, temp = 55 c) ?60 ? a v ih input high voltage 0.7v dd ?vdd+0.2v v il input low voltage ? ? 0.4 v v oh output high voltage (i oh = 2.0 ma) 0.7v dd ?vddv v ol output low voltage (i ol = -2.5 ma) ? ? 0.4 v i il input low leakage current (v in = gnd, no pull-up or pull-down) ??1 a i ih input high leakage current (v in =v dd , no pull-up or pull-down) ??1 a i oh output high current (v oh =0.8v dd , v dd =1.8v) 4.0 ? ? ma i ol output low current (v ol =0.4v, v dd =1.8v) -4.0 ? ? ma i oz output leakage current (v out =v dd , output is high impedance) ??5 a c i input capacitance ? ? 5 pf c o output capacitance ? ? 5 pf table 7. tristate signal timing pin parameter minimum maximum unit tristate time from tristate activate until i/o becomes hi-z ? 20.8 ns table 8. 32k/16m oscillator signal timing parameter minimum rms maximum unit extal32k input jitter (peak to peak) ? 5 20 ns extal32k startup time 800 ? ? ms table 6. maximum and minimum dc characteristics (continued) number or symbol parameter min typical max unit
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 25 4 functional description and application information this section provides the electrica l information including and timing di agrams for the individual modules of the i.mx1. 4.1 embedded trace macrocell all registers in the etm9 are programmed through a jtag interface. th e interface is an extension of the arm920t processor?s tap controller, and is assigned scan chain 6. the scan ch ain consists of a 40-bit shift register comprised of the following: ? 32-bit data field ? 7-bit address field ? a read/write bit the data to be written is scanned in to the 32-bit data field, th e address of the register into the 7-bit address field, and a 1 into the read/write bit. a register is read by scanning its addr ess into the address field and a 0 into the read/write bit. the 32-bit data field is ignored. a read or a write takes place when the tap contro ller enters the update-dr state. the timing diagram for the etm9 is shown in figure 2 . see table 9 for the etm9 timing parameters used in figure 2 . figure 2. trace port timing diagram extal16m input jitter (peak to peak) 1 ?tbdtbd? extal16m startup time 1 tbd ? ? ? 1 the 16 mhz oscillator is not recommended for use in new designs. table 8. 32k/16m oscillator signal timing (continued) parameter minimum rms maximum unit traceclk 4b 4a 3b 2a 1 output trace port 3a valid data valid data 2b traceclk (half-rate clocking mode)
functional description and application information mc9328mx1 technical data, rev. 7 26 freescale semiconductor 4.2 dpll timing specifications parameters of the dpll are given in table 10 . in this table, t ref is a reference clock period after the pre-divider and t dck is the output double clock period. table 9. trace port timing diagram parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 clk frequency 0 85 0 100 mhz 2a clock high time 1.3 ? 2 ? ns 2b clock low time 3 ? 2 ? ns 3a clock rise time ? 4 ? 3 ns 3b clock fall time ? 3 ? 3 ns 4a output hold time 2.28 ? 2 ? ns 4b output setup time 3.42 ? 3 ? ns table 10. dpll specifications parameter test conditions minimum typical maximum unit dpll input clock freq range vcc = 1.8v 5 ? 100 mhz pre-divider output clock freq range vcc = 1.8v 5?30mhz dpll output clock freq range vcc = 1.8v 80 ? 220 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5 ? 15 ? mf integer part ? 5 ? 15 ? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? pre-multiplier lock-in time ? ? ? 312.5 sec freq lock-in time after full reset fol mode for non-integer mf (does not include pre-multi lock-in time) 250 280 (56 s) 300 t ref freq lock-in time after partial reset fol mode for non-integer mf (does not include pre-multi lock-in time) 220 250 (50 s) 270 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-multi lock-in time) 300 350 (70 s) 400 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-multi lock-in time) 270 320 (64 s) 370 t ref freq jitter (p-p) ? ? 0.005 (0.01%) 0.01 2?t dck
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 27 4.3 reset module the timing relationships of the reset module with the por and reset_in are shown in figure 3 and figure 4 . note be aware that nvdd must ramp up to at least 1.8v before qvdd is powered up to prevent forward biasing. figure 3. timing relati onship with por phase jitter (p-p) integer mf, fpl mode, vcc=1.8v ? 1.0 (10%) 1.5 ns power supply voltage ? 1.7 ? 2.5 v power dissipation fol mode, integer mf, f dck = mhz, vcc = 1.8v ?? 4mw table 10. dpll specifications (continued) parameter test conditions minimum typical maximum unit por reset_por reset_dram hreset reset_out clk32 hclk 90% avdd 10% avdd 1 2 3 4 exact 300ms 7 cycles @ clk32 14 cycles @ clk32
functional description and application information mc9328mx1 technical data, rev. 7 28 freescale semiconductor figure 4. timing rela tionship with reset_in 4.4 external interface module the external interface module (eim) handles the interface to devices external to the i.mx1 processor, including the generation of chip-selects for external peripherals and memory. the timi ng diagram for the eim is shown in figure 5 , and table 12 defines the parameters of signals. table 11. reset module timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min max min max 1 width of input power_on_reset note 1 1 por width is dependent on the 32 or 32.768 khz crystal oscilla tor start-up time. design margin should allow for crystal tolerance, i.mx chip variations, temperature impact, and supp ly voltage influence. through t he process of supplying crystals for use with cmos oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. if an external stable clock source (already running) is used instead of a crystal, the width of por should be ignored in calculating timing for the start-up process. ? note 1 ?? 2 width of internal power_on_reset (9600 *clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher fo r sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretcher for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4 ? 4 ? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 29 figure 5. eim bus timing diagram table 12. eim bus timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min typical max min typical max 1a clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns 1b clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns 2a clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns 2b clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns 3a clock fall to read (write ) valid 1.35 2.79 6.52 1.3 2.7 6.3 ns 3b clock fall to read (write ) invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) bclk (burst clock) - rising edge lba (negated falling edge) eb (falling edge) eb (rising edge) bclk (burst clock) - falling edge read data write data (negated falling) write data (negated rising) dtack_b 10a 10a
functional description and application information mc9328mx1 technical data, rev. 7 30 freescale semiconductor 4.4.1 dtack signal description the dtack signal is the external input data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out moni tor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 hclk counts have elapsed. only the cs5 group supports dtack signal function when the external dtack signal is used for data acknowledgement. 4.4.2 dtack signal timing figure 6 through figure 9 show the access cycle timing used by ch ip-select 5. the signa l values and units of measure for this figure are found in the associated tables. 4a clock 1 rise to output enable valid 2.32 2.62 6.85 2.3 2.6 6.8 ns 4b clock 1 rise to output enable invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns 4c clock 1 fall to output enable valid 2.38 2.69 7.04 2.3 2.6 6.8 ns 4d clock 1 fall to output enable invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns 5a clock 1 rise to enable bytes valid 1.91 2.52 5.54 1.9 2.5 5.5 ns 5b clock 1 rise to enable bytes invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns 5c clock 1 fall to enable bytes va lid 1.97 2.59 5.69 1.9 2.5 5.5 ns 5d clock 1 fall to enable bytes in valid 1.76 2.48 5.38 1.7 2.4 5.2 ns 6a clock 1 fall to load burst address valid 2.07 2.79 6.73 2.0 2.7 6.5 ns 6b clock 1 fall to load burst address invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns 6c clock 1 rise to load burst address invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns 7a clock 1 rise to burst clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns 7b clock 1 rise to burst clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns 7c clock 1 fall to burst clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns 7d clock 1 fall to burst clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns 8a read data setup time 5.54 ? ? 5.5 ? ? ns 8b read data hold time 0 ? ? 0 ? ? ns 9a clock 1 rise to write data valid 1.81 2.72 6.85 1.8 2.7 6.8 ns 9b clock 1 fall to write data inva lid 1.45 2.48 5.69 1.4 2.4 5.5 ns 9c clock 1 rise to write data invalid 1.63 ? ? 1.62 ? ? ns 10a dtack setup time 2.52 ? ? 2.5 ? ? ns 1 clock refers to the system clock signal , hclk, generated fr om the system dpll table 12. eim bus timing pa rameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit min typical max min typical max
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 31 4.4.2.1 wait read cycle without dma figure 6. wait read cycle without dma table 13. wait read cycle without dma: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1oe and eb assertion time see note 2 ? ns 2cs5 pulse width 3t ? ns 3oe negated to address inactive 56.81 ? ns 4 wait asserted after oe asserted ? 1020t ns 5 wait asserted to oe negated 2t+2.2 3t+7.17 ns 6 data hold timing after oe negated t-1.86 ? ns 7 data ready after wait asserted 0 t ns 8 oe negated to cs negated 1.5t+0.24 1.5t+0.85 ns 9 oe negated after eb negated 0.5 1.5 ns 10 become low after cs5 asserted 0 1019t ns 11 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the star t of read access cycle. 4. the external wait input requirement is eliminated when cs5 is programmed to use internal wait state. wait address eb cs5 oe databus programmable min 0ns 1 2 3 8 9 5 6 7 11 10 4 x 1)
functional description and application information mc9328mx1 technical data, rev. 7 32 freescale semiconductor 4.4.2.2 wait read cycle dma enabled figure 7. dtack wait re ad cycle dma enabled table 14. dtack wait read cycle dma enab led: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1oe and eb assertion time see note 2 ? ns 2cs pulse width 3t ? ns 3oe negated before cs5 is negated 1.5t+0.24 1.5t+0.85 ns 4 address inactived before cs negated ? 0.93 ns 5 wait asserted after cs5 asserted ? 1020t ns 6wait asserted to oe negated 2t+2.2 3t+7.17 ns 7 data hold timing after oe negated t-1.86 ? ns 8 data ready after wait is asserted ? t ns 9cs deactive to next cs active t ? ns 10 oe negate after eb negate 0.5 1.5 ns 11 wait becomes low after cs5 asserted 0 1019t ns rw wait address eb cs5 oe (logic high) databus programmable min 0ns 1 2 3 8 9 5 6 7 11 10 12 4 n put to m x1)
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 33 4.4.2.3 wait write cycle without dma figure 8. wait write cycle without dma 12 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. oe and eb assertion time is programmable by oea bit in cs5l register. eb assertion in read cycle will occur only when ebc bit in cs5l register is clear. 3. address becomes valid and cs asserts at the star t of read access cycle. 4. the external wait input requirement is eliminated when cs5 is programmed to use internal wait state. table 15. wait write cycle without dma: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1cs5 assertion time see note 2 ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 2.5t-0.29 2.5t+0.68 ns 5rw negated to address inactive 67.28 ? ns 6 wait asserted after cs5 asserted ? 1020t ns table 14. dtack wait read cycle dma enabled: wsc = 111111, dtack_sel=1, hclk=96mhz (continued) number characteristic 3.0 0.3 v unit minimum maximum oe wait address eb cs5 rw (logic high) programmable min 0ns programmable min 0ns 1 2 3 8 9 5 6 7 11 10 12 4 (output from i.mx1) databus
functional description and application information mc9328mx1 technical data, rev. 7 34 freescale semiconductor 4.4.2.4 wait write cycle dma enabled figure 9. wait write cycle dma enabled 7 wait asserted to rw negated 1t+2.15 2t+7.34 ns 8 data hold timing after rw negated 2.5t-1.18 ? ns 9 data ready after cs5 is asserted ? t ns 10 eb negated after cs5 is negated 1.5t+0.74 1.5t+2.35 ns 11 wait becomes low after cs5 asserted 0 1019t ns 12 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (for 96 mhz system clock, t=10.42 ns) 2. cs5 assertion can be controlled by csa bits. eb assertion can also be programmable by wea bits in cs5l register. 3. address becomes valid and rw asserts at the star t of write access cycle. 4. the external wait input requ irement is eliminated when cs5 is programmed to use internal wait state. table 15. wait write cycle without dma: wsc = 111111, dtack_sel=1, hclk=96mhz (continued) number characteristic 3.0 0.3 v unit minimum maximum oe wait address eb cs5 rw (logic high) databus programmable min 0ns programmable min 0ns 8 5 7 11 12 4 1 2 3 10 6 13 9
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 35 4.4.3 eim external bus timing the external interface module (eim) is the interf ace to devices external to the i.mx1, including generation of chip-selects for exte rnal peripherals and memory. the timing diagram for the eim is shown in figure 5 , and table 12 defines the parameters of signals. table 16. wait write cycle dma enabled: wsc = 111111, dtack_sel=1, hclk=96mhz number characteristic 3.0 0.3 v unit minimum maximum 1 cs5 assertion time see note 2 ? ns 2eb assertion time see note 2 ? ns 3cs5 pulse width 3t ? ns 4rw negated before cs5 is negated 2.5t-0.29 2.5t+0.68 ns 5 address inactived after cs negated ? 0.93 ns 6 wait asserted after cs5 asserted ? 1020t ns 7 wait asserted to rw negated t+2.15 2t+7.34 ns 8 data hold timing after rw negated 24.87 ? ns 9 data ready after cs5 is asserted ? t ns 10 cs deactive to next cs active t ? ns 11 eb negate after cs negate 1.5t+0.74 1.5t+2.35 12 wait becomes low after cs5 asserted 0 1019t ns 13 wait pulse width 1t 1020t ns note : 1. t is the system clock period. (f or 96 mhz system clock, t=10.42 ns) 2. cs5 assertion can be controlled by csa bits. eb assertion also can be programmable by wea bits in cs5l register. 3. address becomes valid and rw asserts at the start of write access cycle. 4.the external wait input requ irement is eliminated when cs5 is programmed to use internal wait state.
functional description and application information mc9328mx1 technical data, rev. 7 36 freescale semiconductor figure 10. wsc = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready bclk (burst clock) addr cs2 r/w lba oe ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) data read seq/nonseq v1 last valid data last valid address read v1 v1 v1 internal signals - shown on ly for illustrative purposes note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 37 figure 11. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1) bclk (burst clock) addr cs0 r/w lba oe eb data internal signals - shown onl y for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 38 freescale semiconductor figure 12. wsc = 1, oea = 1, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 0 r/w lba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 39 figure 13. wsc = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data bclk (burst clock) addr cs0 r/w lba oe eb data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 40 freescale semiconductor figure 14. wsc = 3, oea = 2, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs [3] r/w l ba oe data weim_hrdata read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 41 figure 15. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 3 r/w lba oe data weim_hrdata eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 42 freescale semiconductor figure 16. wsc = 3, oea = 4, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe weim_data_in weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 43 figure 17. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data hwdata eb weim_hrdata write nonseq v1 address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data last valid data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 44 freescale semiconductor figure 18. wsc = 3, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 45 figure 19. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read internal signals - shown only for illustrative purposes ebx 1 (ebc 2 =0) ebx 1 (ebc 2 =1) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register
functional description and application information mc9328mx1 technical data, rev. 7 46 freescale semiconductor figure 20. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 47 figure 21. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe weim_hrdata eb data hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 48 freescale semiconductor figure 22. wsc = 2, wws = 2, we a = 1, wen = 2, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 49 figure 23. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 2 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 data hwdata last valid data write data read data write last valid data write data read write idle ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 50 freescale semiconductor figure 24. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data write data (1/2 half word) write data (2/2 half word) hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs r/w lba oe weim_hrdata eb data hwdata last valid data internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 51 figure 25. wsc = 3, cs a = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs 4 r/w l ba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data data hwdata ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 52 freescale semiconductor figure 26. wsc = 2, oea = 2, cnc = 3, bcm = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 read data (v1) address v2 last valid last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2) ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 53 figure 27. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs4 r/w lba oe data weim_hrdata read nonseq v1 address v1 address v8 last valid addr read data last valid data read data hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 54 freescale semiconductor figure 28. wsc = 3, sync = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata nonseq nonse read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 55 figure 29. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 56 freescale semiconductor figure 30. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb address v1 last valid read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 57 figure 31. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 58 freescale semiconductor figure 32. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready bclk (burst clock) addr cs2 r/w lba oe data weim_hrdata ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 ebx 1 (ebc 2 =0) note 1: x = 0, 1, 2 or 3 note 2: ebc = enable byte control bit (bit 11) on the chip select control register ebx 1 (ebc 2 =1) internal signals - shown only for illustrative purposes
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 59 4.4.4 non-tft panel timing figure 33. non-tft panel timing 4.5 pen adc specifications the specifications for the pen adc are shown in table 18 through table 20 . table 17. non tft panel timing diagram symbol parameter allowed register minimum value 1, 2 1 maximum frequency of lcdc_clk is 48 mhz, which is controlled by peripheral clock divider register. 2 maximum frequency of sclk is hclk / 5, otherwise ld output will be wrong. actual value unit t1 hsyn to vsyn delay 3 3 vsyn, hsyn and sclk can be programmed as active high or active low. in the above timing diagram, all these 3 signals are active high. 0hwait2+2 tpix 4 4 tpix is the pixel clock period which equals lcdc_clk period * (pcd + 1). t2 hsyn pulse width 0 hwidth+1 tpix t3 vsyn to sclk ? 0 t3 ts 5 5 ts is the shift clock period. ts = tpix * (panel data bus width). ? t4 sclk to hsyn 0 hwait1+1 tpix table 18. pen adc system performance full range resolution 1 1 tested under input = 0~1.8v at 25c 13 bits non-linearity error 1 4 bits accuracy 1 9 bits t1 t2 t4 t3 xmax vsyn sclk hsyn ld[15:0] t2 t1 ts
functional description and application information mc9328mx1 technical data, rev. 7 60 freescale semiconductor 4.6 asp touch panel controller the following sections contain the electrical specifications of the asp touch panel controller. the value of parameters and their corresponding meas uring conditions are mentioned as well. 4.6.1 electrical specifications test conditions: temperature = 25o c, qvdd = 1800mv. note that qvdd should be 1800mv. table 19. pen adc test conditions vp max 1800 mv ip max +7 a vp min gnd ip min 1.5 a vn gnd in 1.5 a sample frequency 12 mhz sample rate 1.2 khz input frequency 100 hz input range 0?1800 mv note: ru1 = ru2 = 200k table 20. pen adc absolute rating ip max +9.5 a ip min -2.5 a in max +9.5 a in min -2.5 a table 21. asp touch panel controller electrical spec parameter minimum typical maximum unit offset ? 32768 ? ? offset error ? ? 8199 ? gain ? 13.65 ? mv -1 gain error ? ? 33% ? dnl 8 9 ? bits inl ? 0 ? bits accuracy (without missing code) 8 9 ? bits operating voltage range (pen) ? ? qvdd mv operating voltage range (u) negative qvdd ? qvdd mv on-resistance of switches sw[8:1] ? 10 ? ohm
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 61 4.6.2 gain calculations the ideal mapping of input voltage to output digital sample is defined as follows: figure 34. gain calculations in general, the mapping function is: s = g * v + c where v is input, s is output, g is th e slope, and c is the y-intercept. nominal gain g 0 = 65535 / 4800 = 13.65mv -1 nominal offset c 0 = 65535 / 2 = 32767 4.6.3 offset calculations the ideal mapping of input voltage to output digital sample is defined as: figure 35. offset calculations in general, the mapping function is: s = g * v + c where v is input, s is output, g is th e slope, and c is the y-intercept. nominal gain g 0 = 65535 / 4800 = 13.65mv -1 nominal offset c 0 = 65535 / 2 = 32767 2400 1800 smax 65535 c0 g0 sample vi -2400 2400 1800 smax 65535 c0 g0 sample vi -2400
functional description and application information mc9328mx1 technical data, rev. 7 62 freescale semiconductor 4.6.4 gain error calculations gain error calculations are made us ing the information in this section. figure 36. gain error calculations assuming the offset remains unchanged, the mapping is rotated around y-intercept to determine the maximum gain allowed. this occurs when the sample at 1800mv has just reached the ceiling of the 16-bit range, 65535. maximum offset g max, g max = (65535 - c 0) / 1800 = (65535 - 32767) / 1800 = 18.20 gain error g r, g r = (g max - g 0 ) / g 0 * 100% = (18.20 - 13.65) / 13.65 * 100% = 33% 4.7 bluetooth accelerator caution on-chip accelerator hardware is no t supported by software. an external bluetooth chip interfaced to a uart is recommended. the bluetooth accelerator (bta) radio interface supports the wire less rf transceiver, mc13180 using an spi interface. this section provides the data bus timing diagrams and spi interface timing diagrams shown in figure 37 and figure 38 , and the associated parameters shown in table 22 and table 23 . 2400 1800 smax 65535 c0 g0 sample vi - 2400 gmax
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 63 figure 37. mc13180 data bus timing diagram table 22. mc13180 data bus timing parameter table ref no. parameter minimum typical maximum unit 1 framesync setup time relati ve to bt clk rising edge 1 1 please refer to 2.4 ghz rf transceiver module (mc13180) technical data documentation. ?4 ?ns 2 framesync hold time relative to bt clk rising edge 1 ?12 ?ns 3 receive data setup time relative to bt clk rising edge 1 ?6 ?ns 4 receive data hold time rela tive to bt clk rising edge 1 ?13 ?ns 5 transmit data setup time relative to rxtx_en rising edge 2 2 the setup and hold times of rx_tx_en can be adjusted by programming time_a_b register (0x00216050) and rf_status (0x0021605c) registers. 172.5 ? 192.5 s 6 tx data period 1000 +/- 0.02 ns 7 bt clk duty cycle 40 ? 60 % 8 transmit data hold time relative to rxtx_en falling edge 4 ? 10 s bt clk (bt1) fs (bt5) pkt data (bt3) rxtx_en (bt9) pkt data (bt2) 5 4 3 receive transmit 6 7 8 1 2
functional description and application information mc9328mx1 technical data, rev. 7 64 freescale semiconductor figure 38. spi interface ti ming diagram using mc13180 4.8 spi timing diagrams to use the internal transmit (tx) a nd receive (rx) data fifos when the spi 1 module is configured as a master, two control signals are used for data transf er rate control: the ss signal (output) and the spi_rdy signal (input). the spi1 sample period control regi ster (periodreg1) and the spi2 sample period control register (periodreg2) can al so be programmed to a fixed data tr ansfer rate for either spi 1 or spi 2. when the spi 1 module is configured as a slave, the user can configure the spi1 control register (controlreg1) to match the external spi master?s timing. in this configuration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data fifo. figure 39 through figure 43 show the timing relationshi p of the master spi using different triggering mechanisms. table 23. spi interface timing parameter table using mc13180 ref no. parameter minimum maximum unit 1 spi_en setup time relative to rising edge of spi_clk 15 ? ns 2 transmit data delay time relative to rising edge of spi_clk 0 15 ns 3 transmit data hold time relative to rising edge of spi_en 0 15 ns 4 spi_clk rise time 0 25 ns 5 spi_clk fall time 0 25 ns 6 spi_en hold time relative to falling edge of spi_clk 15 ? ns 7 receive data setup time relative to falling edge of spi_clk 1 1 the spi_clk clock frequency and duty cycle, setup and ho ld times of receive data can be set by programming spi_control (0x00216138) register together with system clock. 15 ? ns 8 receive data hold time relative to falling edge of spi_clk 1 15 ? ns 9 spi_clk frequency, 50% duty cycle required 1 ?20mhz spi_en (bt11) spi_data_out (bt12) spi clk (bt13) spi_data_in (bt4) 1 7 4 5 8 2 3 6 9
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 65 figure 39. master spi timing diagram using spi_rdy edge trigger figure 40. master spi timing diagram using spi_rdy level trigger figure 41. master spi timing diagram ignore spi_rdy level trigger figure 42. slave spi timing diagra m fifo advanced by bit count figure 43. slave spi timing di agram fifo advanced by ss rising edge 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso 6 7 ss (input) sclk, mosi, miso
functional description and application information mc9328mx1 technical data, rev. 7 66 freescale semiconductor figure 44. spi sclk timing diagram 4.9 lcd controller this section includes timing diagrams for the lcd c ontroller. for detailed timing diagrams of the lcd controller with various displa y configurations, refer to the lcd controller chapter of the mc9328mx1 reference manual . figure 45. sclk to ld timing diagram table 24. timing parameter table for figure 39 through figure 43 ref no. parameter 3.0 0.3 v unit minimum maximum 1 spi_rdy to ss output low 2t 1 1 t = cspi system clock period (perclk2). ?ns 2ss output low to first sclk edge 3 ? tsclk 2 2 tsclk = period of sclk. ?ns 3 last sclk edge to ss output high 2 ? tsclk ? ns 4ss output high to spi_rdy low 0 ? ns 5ss output pulse width tsclk + wait 3 3 wait = number of bit clocks (sclk) or 32.768 khz clocks per sample period control register. ?ns 6ss input low to first sclk edge t ? ns 7ss input pulse width t ? ns table 25. timing parameter table for spi sclk ref no. parameter 3.0 0.3 v unit minimum maximum 8 sclk frequency 0 10 mhz 9 sclk pulse width 100 ? ns sclk 8 9 9 1 lsclk ld[15:0]
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 67 figure 46. 4/8/16 bit/pixel tft color mode panel timing table 26. lcdc sclk timing parameter table ref no. parameter 3.0 0.3 v unit minimum maximum 1 sclk to ld valid ? 2 ns table 27. 4/8/16 bit/pixel tf t color mode panel timing symbol description minimum corresponding register value unit t1 end of oe to beginning of vsyn t5+t6 +t7+t9 (vwait1t2)+t5+t6+t7+t9 ts t2 hsyn period xmax+5 xm ax+t5+t6+t7+t9+t10 ts t3 vsyn pulse width t2 vwidth(t2) ts t4 end of vsyn to beginning of oe 2 vwait2(t2) ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to t9 1 hwait2+1 ts t7 end of oe to beginning of hsyn 1 hwait1+1 ts line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax vsyn hsyn oe ld[15:0] sclk hsyn oe ld[15:0] t2 t8 vsyn t9 t10 display region non-display line y
functional description and application information mc9328mx1 technical data, rev. 7 68 freescale semiconductor 4.10 multimedia card/secure digital host controller the dma interface block controls al l data routing between the external data bus (dma access), internal mmc/sd module data bus, and inte rnal system fifo a ccess through a dedicated state machine that monitors the status of fifo content (empty or fu ll), fifo address, and byte/block counters for the mmc/sd module (inner system) and th e application (user programming). figure 47. chip-select read cycle timing diagram t8 sclk to valid ld data -3 3 ns t9 end of hsyn idle2 to vsyn edge (for non-display region) 22ts t9 end of hsyn idle2 to vsyn edge (for display region) 11ts t10 vsyn to oe active (sharp = 0) when vwait2 = 0 1 1 ts t10 vsyn to oe active (sharp = 1) when vwait2 = 0 2 2 ts note: ? ts is the sclk period which equals lcdc_c lk / (pcd + 1). normally lcdc_clk = 15ns. ? vsyn, hsyn and oe can be programmed as active hi gh or active low. in figure 46 , all 3 signals are active low. ? the polarity of sclk and ld[ 15:0] can also be programmed. ? sclk can be programmed to be deactivated during the vsyn pulse or the oe deasserted period. in figure 46 , sclk is always active. ? for t9 non-display region, vsyn is non-act ive. it is used as an reference. ? xmax is defined in pixels. table 27. 4/8/16 bit/pixel tft color mode panel timing (continued) symbol description minimum corresponding register value unit bus clock 5b 6b 6a 7 5a 4a 3a 1 cmd_dat input cmd_dat output 4b 3b valid data valid data valid data valid data 2
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 69 4.10.1 command response timing on mmc/sd bus the card identification and card ope ration conditions timing are processe d in open-drain mode. the card response to the host command starts after exactly n id clock cycles. for the card address assignment, set_rca is also processed in the open-drain mode . the minimum delay betw een the host command and card response is ncr clock cycles as illustrated in figure 48 . the symbols for figure 48 through figure 52 are defined in table 29 . table 28. sdhc bus timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 clk frequency at data transfer mode (pp) 1 ?10/30 cards 1 c l 100 pf / 250 pf (10/30 cards) 0 25/5 0 25/5 mhz 2 clk frequency at identification mode 2 2 c l 250 pf (21 cards) 0 400 0 400 khz 3a clock high time 1 ?10/30 cards 6/33 ? 10/50 ? ns 3b clock low time 1 ?10/30 cards 15/75 ? 10/50 ? ns 4a clock fall time 1 ?10/30 cards ? 10/50 (5.00) 3 ? 10/50 ns 4b clock rise time 1 ?10/30 cards ? 14/67 (6.67) 3 ? 10/50 ns 5a input hold time 3 ?10/30 cards 3 c l 25 pf (1 card) 10.3/10.3 ? 9/9 ? ns 5b input setup time 3 ?10/30 cards 10.3/10.3 ? 9/9 ? ns 6a output hold time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 6b output setup time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 7 output delay time 3 0 16 0 14 ns table 29. state signal parameters for figure 48 through figure 52 card active host active symbol definition symbol definition z high impedance state s start bit (0) d data bits t transmitter bit (host = 1, card = 0) * repetition p one-cycle pull-up (1) crc cyclic redundancy check bits (7 bits) e end bit (1)
functional description and application information mc9328mx1 technical data, rev. 7 70 freescale semiconductor figure 48. timing diagrams at identification mode after a card receives its rca, it switches to data transfer mode. as shown on the first diagram in figure 49 , sd_cmd lines in this mode are driven with push-pull drivers. the command is followed by a period of two z bits (allowing time for direction switching on the bus) and then by p bits pushed up by the responding card. the other two diagrams show the separating periods n rc and n cc . figure 49. timing diagrams at data transfer mode figure 50 shows basic read operation timing. in a read ope ration, the sequence starts with a single block read command (which specifies the start address in the argument field). the response is sent on the sd_cmd lines as usual. data transmission from the card star ts after the access time delay n ac , beginning from the last bit of the read command. if the system is in multiple block r ead mode, the card sends a continuous flow of data blocks with distance n ac until the card sees a st op transmission command. the data stops two clock cycles afte r the end bit of the stop command. set_rca timing identification timing host command cid/ocr n id cycles cmd content s t e z z s t content z z ****** crc z host command cid/ocr n cr cycles cmd content s t e z z s t content z z ****** crc z timing of command sequences (all modes) timing response end to next cmd start (data transfer mode) command response timing (data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z z ****** crc z response host command n rc cycles cmd content s t e z z s t content crc e z z ****** crc z host command host command n cc cycles cmd content s t e z z s t content crc e z z ****** crc z
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 71 figure 50. timing diag rams at data read figure 51 shows the basic write operation timing. as with the read ope ration, after the card response, the data transfer starts after n wr cycles. the data is suffix ed with crc check bits to allow the card to check for transmission errors. the card sends back the crc chec k result as a cc status token on the data line. if there was a transmission error, the card sends a ne gative crc status (101); ot herwise, a positive crc status (010) is returned. th e card expects a continuous flow of data bl ocks if it is configured to multiple block mode, with the flow termin ated by a stop transmission command. n ac cycles read data timing of single block read n ac cycles read data timing of multiple block read n ac cycles n st timing of stop command (cmd12, data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc dat z****z z z p p s d ***** d d d dat z****z z z p p s d ***** ****** d d d p ***** p s d d d d ****** host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc ***** read data host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc valid read data dat ***** z z e ***** d d d d d d d d z
functional description and application information mc9328mx1 technical data, rev. 7 72 freescale semiconductor figure 51. timing diagrams at data write the stop transmission command may occur when the card is in different states. figure 52 shows the different scenarios on the bus. write data busy write data write data host command response n cr cycles cmd dat timing of the block write command n wr cycles busy crc status cmd dat timing of the multiple block write command content crc status n wr cycles crc status e z z p p p p ****** z z p p s crc e z z s e z p p s content crc e z z s e s e z x x x x x x l*l x x x x x x status status dat content z z p p s crc e z z x x z p p s content crc e z z x x x x x x x x x x z n wr cycles x x x x x x z****z z z z p p s content crc e z z s e s e z l*l status x x x x x x x z x x x e z z p p s content crc z z z dat z****z content s t crc e z z p p s t content crc e z z p ****** ****** p p p
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 73 figure 52. stop transmission during different scenarios table 30. timing values for figure 48 through figure 52 parameter symbol minimum maximum unit mmc/sd bus clock, clk (all values are refe rred to minimum (vih) and maximum (vil) command response cycle ncr 2 64 clock cycles identificati on response cycle nid 5 5 clock cycles access time delay cycle nac 2 taac + nsac clock cycles write data stop transmission during data transfer from the host. busy (card is programming) stop transmission during crc status transfer from the card. stop transmission received a fter last data block. card becomes busy programming. stop transmission received a fter last data block. card becomes busy programming. host command card response n cr cycles cmd content s t e z z p p s t content crc e z z ****** host command content s t crc e dat ****** d d d d d d z z z z d d d d d d d e z z s l z z z z z z z z z z z z z z z z z z z z z z e dat ****** d d d d d d z z z z d z z s z z s l z z z z z z z z z z z z z z z z z z z z z z e crc e crc dat ****** s l z z z z z z z z z z z z z z z z z z z z z z z z z z e dat ****** z z z z z z z z z z z z z z z z z z z z s l z z z z z z z z z z z z z z z z z z z z z z e z
functional description and application information mc9328mx1 technical data, rev. 7 74 freescale semiconductor 4.10.2 sdio-irq and readwait service handling in sdio, there is a 1-bit or 4-bi t interrupt response from the sdio peripheral card. in 1-bit mode, the interrupt response is simply that the sd_dat[1] line is held low. the sd_dat[1] line is not used as data in this mode. the memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (s d_dat[1] returns to its high level). in 4-bit mode, the interrupt is less simple. the interrupt triggers at a pa rticular period call ed the ?interrupt period? during the data access, and the controller must sample sd_dat[1] during this short period to determine the irq status of the attached card. the interrupt period only happens at the boundary of each block (512 bytes). figure 53. sdio irq timing diagram readwait is another feature in sdio that allows the user to submit commands during the data transfer. in this mode, the block temporarily pauses the data tr ansfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as nor mal. after all comm ands are submitted, the user can switch back to the da ta transfer operation and all counter and status values are resumed as access continues. command read cycle nrc 8 ? clock cycles command-command cycl e ncc 8 ? clock cycles command write cycl e nwr 2 ? clock cycles stop transmission cycle nst 2 2 clock cycles taac: data read access time -1 def ined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104] table 30. timing values for figure 48 through figure 52 (continued) parameter symbol minimum maximum unit interrupt period irq irq dat[1] for 4-bit l h interrupt period dat[1] for 1-bit cmd content s t e z z p e z z ****** z z response crc s z z e s block data e s block data
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 75 figure 54. sdio readwa it timing diagram 4.11 memory stick host controller the memory stick protocol requires three interface signal line connect ions for data transfers: ms_bs, ms_sdio, and ms_sclko. communication is always initiated by the mshc and operates the bus in either four-state or two-state access mode. the ms_bs signal classifies data on the sdio into one of four st ates (bs0, bs1, bs2, or bs3) according to its attribute and transfer dire ction. bs0 is the int transfer stat e, and during this state no packet transmissions occur. during the bs 1, bs2, and bs3 states, packet co mmunications are executed. the bs1, bs2, and bs3 states are regarded as one packet length and one communicati on transfer is always completed within one packet le ngth (in four-state access mode). the memory stick usually operates in four state access mode and in bs 1, bs2, and bs3 bus states. when an error occurs during packet commu nication, the mode is shifted to two-state access mode, and the bs0 and bs1 bus states are automatically repeat ed to avoid a bus collision on the sdio. dat[1] for 4-bit dat[2] for 4-bit cmd ****** p s t e z z ****** cmd52 z crc e z z s block data l l l l l l l l l l l l l l l l l l l l l h z s e s block data e block data z z l h e s block data
functional description and application information mc9328mx1 technical data, rev. 7 76 freescale semiconductor figure 55. mshc signal timing diagram table 31. mshc signal timing parameter table ref no. parameter 3.0 0.3 v unit minimum maximum 1 ms_sclki frequency ? 25 mhz 2 ms_sclki high pulse width 20 ? ns 3 ms_sclki low pulse width 20 ? ns 4 ms_sclki rise time ? 3 ns 5 ms_sclki fall time ? 3 ns 6 ms_sclko frequency 1 ?25mhz 7 ms_sclko high pulse width 1 20 ? ns 8 ms_sclko low pulse width 1 15 ? ns 9 ms_sclko rise time 1 ?5ns 10 ms_sclko fall time 1 ?5ns 11 ms_bs delay time 1 ?3ns ms_sclko 11 ms_bs ms_sdio(output) ms_sdio (input) ms_sdio (input) 11 12 12 13 14 15 16 (red bit = 0) (red bit = 1) ms_sclki 1 6 2 3 7 8 4 5 9 10
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 77 4.12 pulse-width modulator the pwm can be programmed to select one of two clock signals as it s source frequency. the selected clock signal is passed through a divi der and a prescaler before being i nput to the counter. the output is available at the pulse-width modul ator output (pwmo) external pi n. its timing diagram is shown in figure 56 and the parameters are listed in table 32 . figure 56. pwm output timing diagram 12 ms_sdio output delay time 1,2 ?3ns 13 ms_sdio input setup time for ms_sclko rising edge (red bit = 0) 3 18 ? ns 14 ms_sdio input hold time for ms_sclko rising edge (red bit = 0) 3 0?ns 15 ms_sdio input setup time for ms_sclko falling edge (red bit = 1) 4 23 ? ns 16 ms_sdio input hold time for ms_sclko falling edge (red bit = 1) 4 0?ns 1 loading capacitor condition is less than or equal to 30pf. 2 an external resistor (100 ~ 200 ohm) should be inserted in series to provide current c ontrol on the ms_sdio pin, because of a possibility of signal conflict between the ms_sdio pin and memory stick sdio pin when the pin direction changes. 3 if the msc2[red] bit = 0, mshc samples ms_s dio input data at ms_sclko rising edge. 4 if the msc2[red] bit = 1, mshc samples ms_sdi o input data at ms_sclko falling edge. table 32. pwm output timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 system clk frequency 1 0870100mhz 2a clock high time 1 3.3 ? 5/10 ? ns 2b clock low time 1 7.5 ? 5/10 ? ns 3a clock fall time 1 ?5?5/10ns table 31. mshc signal timing parameter table (continued) ref no. parameter 3.0 0.3 v unit minimum maximum system clock 2a 1 pwm output 3b 2b 3a 4b 4a
functional description and application information mc9328mx1 technical data, rev. 7 78 freescale semiconductor 4.13 sdram controller this section shows timing diagrams and paramete rs associated with th e sdram (synchronous dynamic random access memory) controller. figure 57. sdram read cycle timing diagram 3b clock rise time 1 ?6.67?5/10ns 4a output delay time 1 5.7 ? 5 ? ns 4b output setup time 1 5.7 ? 5 ? ns 1 c l of pwmo = 30 pf table 32. pwm output timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum sdclk cs cas we addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6 note: cke is high during the read/write cycle. ras
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 79 table 33. sdram read timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 3s cs, ras, cas, we, dqm setup time 3.42 ? 3 ? ns 3h cs, ras, cas, we, dqm hold time 2.28 ? 2 ? ns 4s address setup time 3.42 ? 3 ? ns 4h address hold time 2.28 ? 2 ? ns 5 sdram access time (cl = 3) ? 6.84 ? 6 ns 5 sdram access time (cl = 2) ? 6.84 ? 6 ns 5 sdram access time (cl = 1) ? 22 ? 22 ns 6 data out hold time 2.85 ? 2.5 ? ns 7 data out high-impedance time (cl = 3) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 2) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 1) ? 22 ? 22 ns 8 active to read/write command period (rc = 1) t rcd 1 1 t rcd = sdram clock cycle time. this settings can be found in the mc9328mx1 reference manua l. ?t rcd1 ?ns
functional description and application information mc9328mx1 technical data, rev. 7 80 freescale semiconductor figure 58. sdram write cycle timing diagram table 34. sdram write timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period 1 1 precharge cycle timing is included in the write timing diagram. t rp 2 2 t rp and t rcd = sdram clock cycle time. these settings can be found in the mc9328mx1 reference manual . ?t rp2 ?ns 7 active to read/write command delay t rcd2 ?t rcd2 ?ns 8 data setup time 4.0 ? 2 ? ns 9 data hold time 2.28 ? 2 ? ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 81 figure 59. sdram refresh timing diagram table 35. sdram refresh timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period t rp 1 1 t rp and t rc = sdram clock cycle time. these settings can be found in the mc9328mx1 reference manual . ?t rp1 ?ns 7 auto precharge command period t rc1 ?t rc1 ?ns sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7
functional description and application information mc9328mx1 technical data, rev. 7 82 freescale semiconductor figure 60. sdram self-refresh cycle timing diagram 4.14 usb device port four types of data transfer modes exist for the usb module: control tr ansfers, bulk transfers, isochronous transfers, and interrupt transfers. from the perspective of the usb modul e, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. this section covers the transfer modes and how they work from the ground up. data moves across the usb in packets. groups of packets are combined to form data transfers. the same packet transfer mechanism applies to bulk, interrupt, and cont rol transfers. isochronou s data is also moved in the form of packets, however, because isoc hronous pipes are given a fixed portion of the usb bandwidth at all times, there is no end-of-transfer. sdclk cs cas ras addr dq dqm ba we cke
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 83 figure 61. usb device timing diagram for data transfer to usb transceiver (tx) table 36. usb device timing parameters for data transfer to usb transceiver (tx) ref no. parameter 3.0 0.3 v unit minimum maximum 1t roe_vpo ; usbd_roe active to usbd_vpo low 83.14 83.47 ns 2t roe_vmo ; usbd_roe active to usbd_vmo high 81.55 81.98 ns 3t vpo_roe ; usbd_vpo high to usbd_roe deactivated 83.54 83.80 ns 4t vmo_roe ; usbd_vmo low to usbd_roe deactivated (includes se0) 248.90 249.13 ns 5t feopt ; se0 interval of eop 160.00 175.00 ns 6t period ; data transfer rate 11.97 12.03 mb/s usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) usbd_suspnd (output) usbd_rcv (input) usbd_vp (input) usbd_vm (input) t roe_vpo t vmo_roe t vpo_roe t feopt t roe_vmo t period 1 2 3 4 5 6
functional description and application information mc9328mx1 technical data, rev. 7 84 freescale semiconductor figure 62. usb device timing diagram for data transfer from usb transceiver (rx) 4.15 i 2 c module the i 2 c communication protocol consists of seven el ements: start, data source/recipient, data direction, slave acknowledge, data , data acknowledge, and stop. figure 63. definition of bus timing for i 2 c table 37. usb device timing parameter table for data transfer from usb transceiver (rx) ref no. parameter 3.0 0.3 v unit minimum maximum 1t feopr ; receiver se0 interval of eop 82 ? ns usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) (output) usbd_suspnd (input) usbd_vp usbd_rcv (input) usbd_vm (input) t feopr 1 sda scl 1 2 3 4 6 5
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 85 4.16 synchronous serial interface the transmit and receive sections of the ssi can be synchronous or asynchronous. in synchronous mode, the transmitter and the receiver use a common clock and frame sync hronization signal. in asynchronous mode, the transmitter and receive r each have their own clock a nd frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock r uns continuously. in gated clock mode, the clock functions only during transmission. the internal and external clock timing diagrams are shown in figure 65 through figure 67 . normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-tim e division multiplex networks with ot her processors or codecs, allowing interface to time division multiple xed networks without additional logi c. use of the gated clock is not allowed in network mode. these distinctions result in the basic operating modes that allow the ssi to communicate with a wide variety of devices. figure 64. ssi transmitter internal clock timing diagram table 38. i 2 c bus timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum 1 hold time (repeated) start condition 182 ? 160 ? ns 2 data hold time 01710150ns 3 data setup time 11.4 ? 10 ? ns 4 high period of the scl clock 80 ? 120 ? ns 5 low period of the scl clock 480 ? 320 ? ns 6 setup time for stop condition 182.4 ? 160 ? ns stck output stfs (bl) output stfs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 note: srxd input in synchronous mode only.
functional description and application information mc9328mx1 technical data, rev. 7 86 freescale semiconductor figure 65. ssi receiver internal clock timing diagram figure 66. ssi transmitter exte rnal clock timing diagram srck output srfs (bl) output srfs (wl) output 3 7 srxd input 13 14 1 5 9 stck input 16 stfs (bl) input stfs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only 33 20 15
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 87 figure 67. ssi receiver exte rnal clock timing diagram table 39. ssi (port c primary function) timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum internal clock operation 1 (port c primary function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.54.51.33.9ns 3 srck high to srfs (bl) high 3 -1.2 -1.7 -1.1 -1.5 ns 4 stck high to stfs (bl) low 3 2.54.32.23.8ns 5 srck high to srfs (bl) low 3 0.1 -0.8 0.1 -0.8 ns 6 stck high to stfs (wl) high 3 1.48 4.45 1.3 3.9 ns 7 srck high to srfs (wl) high 3 -1.1 -1.5 -1.1 -1.5 ns 8 stck high to stfs (wl) low 3 2.51 4.33 2.2 3.8 ns 9 srck high to srfs (wl) low 3 0.1 -0.8 0.1 -0.8 ns 10 stck high to stxd valid from high impedance 14.25 15.73 12.5 13.8 ns 11a stck high to stxd high 0.91 3.08 0.8 2.7 ns 11b stck high to stxd low 0.57 3.19 0.5 2.8 ns 12 stck high to stxd high impedance 12.88 13.57 11.3 11.9 ns 13 srxd setup time before srck low 21.1 ? 18.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port c primary function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns srck input 16 srfs (bl) input srfs (wl) input 17 19 23 srxd input 29 30 21 25 15
functional description and application information mc9328mx1 technical data, rev. 7 88 freescale semiconductor 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.01 28.16 15.8 24.7 ns 27a stck high to stxd high 8.98 18.13 7.0 15.9 ns 27b stck high to stxd low 9.12 18.24 8.0 16.0 ns 28 stck high to stxd high impedance 18.47 28.5 16.2 25.0 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns synchronous internal clock operation (port c primary function 2 ) 31 srxd setup before stck falling 15.4 ? 13.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port c primary function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1 all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the cloc k and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. 2 there are 2 sets of i/o signals for the ssi module. they are fr om port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288). when ssi signals are conf igured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are c onfigured as input, the ssi mo dule selects the input based on status of the fmcr register bits in t he clock controller module (crm). by default, the input are selected from port c primary function. 3 bl = bit length; wl = word length. table 39. ssi (port c primary function) timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 89 table 40. ssi (port b alternate fun ction) timing parameter table ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum internal clock operation 1 (port b altern ate function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.1 1.0 -0.1 1.0 ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.1 1.0 -0.1 1.0 ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from high impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port b alternate function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns
functional description and application information mc9328mx1 technical data, rev. 7 90 freescale semiconductor 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hold time after srck low 0 ? 0 ? ns synchronous internal clock operation (port b alternate function 2 ) 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port b alternate function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1 all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. 2 there are 2 set of i/o signals for the ssi module. they are fr om port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288). when ssi signals are configured as outputs, th ey can be viewed both at port c primary function and port b alternate function. when ssi signals are conf igured as inputs, the ssi module selects the input based on fmcr register bits in the clock controll er module (crm). by default, the input ar e selected from port c primary function. 3 bl = bit length; wl = word length. table 41. ssi 2 (port c alternate function) timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port c alternate function) 2 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.11.0-0.11.0ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.11.0-0.11.0ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from hi gh impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns table 40. ssi (port b alternate function) timing parameter table (continued) ref no. parameter 1.8 0.1 v 3.0 0.3 v unit minimum maximum minimum maximum
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 91 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14srxd hold time after srck low 0?0?ns external clock operation (port c alternate function) 2 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ?92.8081.4ns 19 srck high to srfs (bl) high 3 ?92.8081.4ns 20 stck high to stfs (bl) low 3 ?92.8081.4ns 21 srck high to srfs (bl) low 3 ?92.8081.4ns 22 stck high to stfs (wl) high 3 ?92.8081.4ns 23 srck high to srfs (wl) high 3 ?92.8081.4ns 24 stck high to stfs (wl) low 3 ?92.8081.4ns 25 srck high to srfs (wl) low 3 ?92.8081.4ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30srxd hole time after srck low 0?0?ns synchronous internal clock operation (port c alternate function) 2 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32srxd hold after stck falling 0?0?ns synchronous external clock operation (port c alternate function) 2 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34srxd hold after stck falling 0?0?ns 1 all the timings for both ssi modules are given for a non-inve rted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the fram e sync stfs/srfs shown in the tables and in the figures. table 41. ssi 2 (port c alternate functi on) timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum
functional description and application information mc9328mx1 technical data, rev. 7 92 freescale semiconductor 4.17 cmos sensor interface the cmos sensor interface (csi) m odule consists of a cont rol register to confi gure the interface timing, a control register for statisti c data generation, a status re gister, interface logic, a 32 32 image data receive fifo, and a 16 32 statistic data fifo. 4.17.1 gated clock mode figure 68 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on the positive edge. figure 69 shows the timing diagram when the cmos sensor output data is configured for positiv e edge and the csi is programmed to received data in negative edge. the parameters for the timing diagrams are listed in table 42 . figure 68. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge 2 there is one set of i/o signals for the ssi2 module. they are from port c alternate function (pc19 ? pc24). when ssi signals are configured as outputs, they can be viewed at port c alter nate function a. when ssi signals are configured as inputs, the ssi module selects the input based on fmcr register bits in t he clock controller module (crm). by default, the input is selecte d from port c alternate function. 3 bl = bit length; wl = word length vsync hsync pixclk data[7:0] valid data valid data 2 1 7 5 6 3 4 valid data
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 93 figure 69. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge the limitation on pixel clock rise time / fall time ar e not specified. it should be calculated from the hold time and setup time, according to: rising-edge latch data max rise time allowed = (pos itive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cy cle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns table 42. gated clock mode timing parameters ref no. parameter min max unit 1 csi_vsync to csi_hsync 180 ? ns 2 csi_hsync to csi_pixclk 1 ? ns 3 csi_d setup time 1 ? ns 4 csi_d hold time 1 ? ns 5 csi_pixclk high time 10.42 ? ns 6 csi_pixclk low time 10.42 ? ns 7 csi_pixclk frequency 0 48 mhz vsync hsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6 7
functional description and application information mc9328mx1 technical data, rev. 7 94 freescale semiconductor falling-edge latch data max fall time allowed = (neg ative duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) 4.17.2 non-gated clock mode figure 70 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on the positive edge. figure 71 shows the timing diagram when the cmos sensor output data is configured for positiv e edge and the csi is programmed to received data in negative edge. the parameters for the timing diagrams are listed in table 43 . figure 70. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge figure 71. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge table 43. non-gated clock mode parameters ref no. parameter min max unit 1 csi_vsync to csi_pixclk 180 ? ns 2 csi_d setup time 1 ? ns vsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6 vsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6
functional description and application information mc9328mx1 technical data, rev. 7 freescale semiconductor 95 the limitation on pixel clock rise time / fall time ar e not specified. it should be calculated from the hold time and setup time, according to: max rise time allowed = (pos itive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cy cle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns falling-edge latch data max fall time allowed = (neg ative duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) 3 csi_d hold time 1 ? ns 4 csi_pixclk high time 10.42 ? ns 5 csi_pixclk low time 10.42 ? ns 6 csi_pixclk frequency 0 48 mhz table 43. non-gated clock mode parameters (continued) ref no. parameter min max unit
mc9328mx1 technical data, rev. 7 96 freescale semiconductor pin-out and package information 5 pin-out and package information table 44 illustrates the package pin assignments for the 256-pin mapbga packag e. for a complete listing of signals, see the signal multiplexing table 3 on page 11. table 44. i.mx1 256 mapbga pin assignments 12345678910111213141516 a nvss sd_dat3 sd_clk nvss usbd_ afe nvdd4 nvss uart1_ rts uart1_ rxd nvdd3 bt5 bt3 qvdd4 rvp uip n.c. a b a24 sd_dat1 sd_cmd sim_tx usbd_ roe usbd_vp ssi_rxclk ssi_txclk spi1_ sclk bt11 bt7 bt1 qvss rvm uin n.c. b c a23 d31 sd_dat0 sim_pd usbd_ rcv uart2_ cts uart2_ rxd ssi_ rxfs uart1_ txd btrfgnd bt8 btrfvdd n.c. avdd2 1 1 asp signals are clamped by avdd2 to prevent esd (electrostatic discharge) damage. av dd2 must be greater t han qvdd to keep diode s reversed-biased. vss r1b c d a22 d30 d29 sim_sven usbd_ suspnd usbd_ vpo usbd_ vmo ssi_rxdat spi1_ spi_rdy bt13 bt6 n.c. n.c. n.c. r1a r2b d e a20 a21 d28 d26 sd_dat2 usbd_vm uart2_ rts ssi_txdat spi1_ss bt12 bt4 n.c. n.c. py2 px2 r2a e f a18d27d25a19a16sim_rst uart2_ txd ssi_txfs spi1_ miso bt10 bt2 rev py1 px1 lsclk spl_spr f g a15 a17 d24 d23 d21 sim_rx sim_clk uart1_ cts spi1_ mosi bt9 cls contrast acd/oe lp/ hsync flm/ vsync ld1 g h a13 d22 a14 d20 nvdd1 nvdd1 nvss qvss qvdd1 ps ld0 ld2 ld4 ld5 ld9 ld3 h j a12 a11 d18 d19 nvdd1 nvdd1 nvss nvdd1 n vss nvss ld6 ld7 ld8 ld11 qvdd3 qvss j k a10 d16 a9 d17 nvdd1 nvss nvss nvdd1 nvdd2 nvdd2 ld10 ld12 ld13 ld14 tmr2out ld15 k l a8 a7 d13 d15 d14 nvdd1 nvss cas tck tin pwmo csi_mclk csi_ d0 csi_d1 csi_d2 csi_d3 l m a5 d12 d11 a6 sdclk nvss rw ma10 ras reset_in big_ endian csi_d4 csi_ hsync csi_vsync csi_d6 csi_d5 m n a4 eb1 d10d7a0d4pa17d1dqm1 reset_sf 2 2 this signal is not used and should be floated in an actual application. reset_ out boot2 csi_ pixclk csi_d7 tms tdi n p a3 d9 eb0 cs3 d6 ecb d2 d3 dqm3 sdcke1 boot3 boot0 trst i2c_scl i2c_sda xtal32k p r eb2 eb3 a1 cs4 d8 d5 lba bclk 3 3 burst clock d0 dqm0 sdcke0 por boot1 tdo qvdd2 extal32k r t nvss a2 oe cs5 cs2 cs1 cs0 ma11 dqm2 sdwe clko avdd1 tristate extal16m xtal16m qvss t 12345678910111213141516
pin-out and package information mc9328mx1 technical data, rev. 7 freescale semiconductor 97 5.1 mapbga 256 package dimensions figure 72 illustrates the 256 mapbga 14 mm 14 mm 1.30 mm package, with an 0.8 mm pad pitch. the device designator for the mapbga package is vh. figure 72. i.mxl 256 mapbga mechanical drawing notes: 1. all dimensions are in millimeters. 2.interpret dimensions and tolerances per asme y14 5m-1994. 3.maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plan e is defined by spherical crowns of the solder balls. case outline 1367 side view bottom view top view
product documentation mc9328mx1 technical data, rev. 7 98 freescale semiconductor 6 product documentation 6.1 revision history table 45 provides revision history for this release. this history includes technical content revisions only and not stylistic or grammatical changes. 6.2 reference documents the following documents ar e required for a complete descripti on of the mc9328mx1 and are necessary to design properly with the device. especially for those not familiar with the arm920t processor or previous i.mx processor products, the following documen ts are helpful when used in conjunction with this document. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) arm technical reference manual (arm ltd., order number arm ddi 0151c) emt9 technical reference manual (arm ltd., order number ddi o157e) mc9328mx1 product brief (order number mc9328mx1p) mc9328mx1 reference manual (order number mc9328mx1rm) the freescale manuals are available on th e freescale semiconducto rs web site at http://www.freescale.com/imx. th ese documents may be downloaded directly from the freescale web site, or printed versions may be ordered. the arm ltd. documentation is available from http://www.arm.com. table 45. i.mx1 data sheet revision history rev. 7 location revision table 1 on page 3 signal names and descriptions ? added the dma_req signal to table. ? corrected signal name from usbd_oe to usbd_roe ? corrected signal names from: c10 btrfgn, to: btrfgnd from: g6 sim_rst, to: sim_rx from: g7 uart2_txd, to: sim_clk table 3 on page 11 signal multiplex table i.mx1 added signal multiplex table from reference manual with the following changes: ? changed i/o supply voltage, pb31?14, from nvdd3 to nvdd4 ? corrected footnotes 1?5. ? changed avdd2 references to qvdd, except for c14. added footnote regarding esd. ? changed occurrence of sd_sclk to sd_clk. ? removed 69k pull-up resistor from eb1, eb2, and added to d9 table 10 on page 26 changed first and second parameters descriptions: from: reference clock freq range, to: dpll input clock freq range from: double clock freq range, to: dpll output freq range table 3 on page 11 added signal multiplex table.
notes mc9328mx1 technical data, rev. 7 freescale semiconductor 99
document number: mc9328mx1 rev. 7 12/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. arm and the arm powered logo are the registered trademarks of arm limited. arm9, arm920t, and arm9tdmi are the trademarks of arm limited. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. rohs-compliant and/or pb-free versions of freesc ale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp.

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